Solid-State Field Guide
Semiconductor & Electronics Theory for Electronic Engineers

Semiconductor behaviour is fundamentally quantum mechanical — classical physics cannot explain why silicon conducts and glass does not, why transistors amplify, or why tunnel currents leak through gate oxides. The key quantum ideas for EEs: wave-particle duality — electrons have both particle and wave properties, characterised by de Broglie wavelength λ = h/p ≈ 0.5–1 nm in silicon. Quantised energy levels — electrons can only occupy discrete energy states; in a crystal, these merge into bands. Pauli exclusion principle — no two electrons can share the same quantum state; this forces electrons to fill states from the lowest energy up, determining the Fermi distribution. Tunnelling — electrons have a nonzero probability of penetrating potential barriers thinner than their wave function extent (~3 nm for gate oxides). These concepts are not academic — they drive every 7 nm and below CMOS design decision.

When atoms bond in a crystal, their discrete energy levels split and broaden into continuous energy bands due to quantum mechanical coupling. The valence band (filled at 0 K — electrons tightly bound) and conduction band (empty at 0 K — electrons can move freely) are separated by a bandgap Eg where no electron states exist. Conductors: bands overlap — electrons freely move at any temperature. Insulators: Eg ≫ kT — valence band full, conduction band inaccessible. Semiconductors: Eg ≈ 1–2 eV — thermal energy (kT ≈ 26 meV at 300 K) promotes a small but controllable number of electrons across the gap, creating mobile electron-hole pairs. The genius of silicon technology is that this conductivity can be precisely controlled by doping and electric fields — from near-insulator to near-conductor on demand.

The Fermi level Ef is the energy at which the probability of occupation is exactly 50% — it is the electrochemical potential of electrons. It is not a real state (it lies in the bandgap for semiconductors) but a statistical descriptor that determines everything about carrier populations. For a non-degenerate semiconductor: n·p = nᵢ² regardless of doping — the mass-action law. Moving Ef closer to Ec increases n (n-type behaviour); moving it toward Ev increases p (p-type). At equilibrium, Ef is spatially constant — any spatial gradient in Ef drives a current. In a circuit, applied voltage directly shifts the local Fermi level — current flows because V ∝ ΔEf/q. The Fermi level is voltage expressed in electron-energy units.

Intrinsic semiconductor: pure crystal, equal electron and hole concentrations (nᵢ ≈ 1.5×10¹⁰ cm⁻³ for Si at 300 K). Too resistive for most applications (~2300 Ω·cm). Extrinsic: doped with impurities that donate extra electrons (n-type) or create holes (p-type). The mass-action law n·p = nᵢ² always holds in thermal equilibrium — if you add electrons (donors), holes are suppressed, and vice versa. The majority carrier concentration approximately equals the dopant concentration (for typical doping levels): n-type with Nd = 10¹⁷ cm⁻³ gives n ≈ 10¹⁷ cm⁻³ and p = (1.5×10¹⁰)²/10¹⁷ ≈ 2250 cm⁻³ — 13 orders of magnitude fewer holes. This extreme asymmetry is the basis of p-n junction rectification and transistor action.

Doping replaces a small fraction of silicon atoms (group IV) with impurities from adjacent groups. Donors (phosphorus, arsenic, antimony) have 5 valence electrons — after bonding with silicon's 4, one electron is loosely bound with ionisation energy ~50 meV (easily freed at room temperature where kT = 26 meV). Acceptors (boron) have 3 valence electrons — accept an electron from a nearby Si-Si bond, creating a hole. Compensation: if both donors and acceptors are present, they partially cancel — net doping is |Nd − Na|, mobility is reduced (more scattering centres). This is how CMOS devices are made — both n-type and p-type regions on the same substrate via selective doping using ion implantation, where dopant atoms are literally shot into the silicon at controlled energies and doses.

Two mechanisms drive carrier current: Drift — carriers accelerated by an electric field, reaching a terminal drift velocity v_d = μE (mobility times field). At low fields, velocity is proportional to field. At high fields (~10⁵ V/cm in Si), velocity saturates at v_sat ≈ 10⁷ cm/s as carriers scatter from optical phonons — a critical limitation for short-channel devices. Diffusion — carriers flow from high to low concentration proportional to the gradient. The Einstein relation D = μVₜ links both mechanisms through the same microscopic scattering physics. Electrons are roughly 3× more mobile than holes in silicon — this is why n-channel MOSFETs (driven by electron current) are faster and more power-efficient than p-channel for the same geometry.

The continuity equation tracks the local carrier population: carriers are created (generation G), destroyed (recombination), and transported (current divergence). Minority carrier lifetime τ is how long an injected carrier survives before recombining — it determines transistor speed and efficiency. In a BJT base: minority carriers must diffuse across the base width W_B before recombining; transit time τ_transit = W_B²/(2Dₙ) sets the speed. Diffusion length L = √(Dτ) — the average distance a minority carrier travels before recombining. Key design insight: base width must be W_B ≪ L_n for high BJT current gain β. Similarly, solar cell efficiency requires diffusion lengths much greater than the absorption depth.

When electron-hole pairs recombine, the electron drops from conduction band to valence band, releasing energy as a photon (radiative) or phonon (non-radiative). Shockley-Read-Hall (SRH) recombination dominates in silicon — carriers recombine via energy states deep in the bandgap introduced by impurities or crystal defects. This is why silicon is a poor light emitter (indirect bandgap) and why crystal purity and surface passivation are critical for solar cells and transistor leakage. Radiative recombination dominates in direct-bandgap materials (GaAs, InGaAs, GaN) — exploited in LEDs and laser diodes. Auger recombination becomes significant at high carrier densities (> 10¹⁸ cm⁻³) — limits efficiency of power devices and laser diodes at high injection.

When p-type and n-type silicon contact each other, electrons diffuse from n into p, holes from p into n. Ionised dopants left behind create a depletion region with a built-in electric field that opposes further diffusion. Equilibrium is reached when drift and diffusion currents exactly cancel — Fermi level becomes spatially flat. The built-in potential V_bi represents the band bending across the junction — it is not directly measurable externally (contact potentials compensate exactly), but it controls junction behaviour. The depletion width W_dep extends farther into the lighter-doped side (charge neutrality: Na·xₚ = Nd·xₙ). Every p-n junction — every diode, transistor junction, solar cell — rests on these equilibrium foundations.

The Shockley equation is derived by solving the minority carrier continuity equation across the depletion region with boundary conditions set by the applied voltage (which modifies the carrier concentrations at the edges of the depletion region). Forward bias (V > 0): reduces the built-in barrier, injecting minority carriers — current rises exponentially. At room temperature, each 60 mV increase in forward voltage increases current 10×. Reverse bias (V < 0): the exponential saturates at −I₀, a tiny leakage current. The ideality factor n = 1 for diffusion-dominated current, n = 2 for recombination-generation in the depletion region (dominant at low forward voltages). Real diodes show n ≈ 1.5–2 at low currents and n → 1 at moderate currents. Temperature dependence: I₀ ∝ nᵢ² ∝ exp(−Eg/kT) — junction voltage drops ~2 mV/°C at constant current.

A p-n junction exhibits two types of capacitance that dominate high-frequency behaviour. Depletion capacitance C_j: the depletion region acts as a parallel-plate capacitor (charge = ionised dopants, dielectric = depleted silicon). It decreases with reverse bias (depletion widens) — exploited in varactor diodes for voltage-controlled tuning in PLLs and RF oscillators. Under forward bias, C_j increases rapidly and becomes less meaningful. Diffusion capacitance C_d: forward-biased minority carriers stored in the quasi-neutral regions represent charge that must be supplied or extracted during switching — C_d = τ·gₘ, proportional to operating current and lifetime. This is the dominant capacitance in forward-biased BJTs and sets base transit time. Diode switching speed is limited by minority charge storage — the origin of reverse recovery time t_rr in fast rectifiers.

At sufficiently high reverse voltage, the junction E-field becomes large enough to initiate breakdown — a sudden increase in current. Avalanche breakdown: carriers gain enough kinetic energy from the field (E ≈ 3×10⁵ V/cm in Si) to ionise Si-Si bonds on impact, creating additional electron-hole pairs, which are themselves accelerated to create more pairs — a multiplicative chain reaction. Avalanche is the mechanism for most rectifier diodes and TVS (transient voltage suppressor) devices. V_BR increases with temperature (carriers scatter more, need higher field to ionise). Zener breakdown: direct quantum-mechanical tunnelling of electrons through the thin depletion barrier — dominant at V < ~4 V (high doping, thin junction). Decreases with temperature. Between 4–6 V, both mechanisms contribute — giving near-zero temperature coefficient (exploited for precision 5.1 V reference diodes).

The BJT is a current-controlled device based on minority carrier injection. Physics of operation: forward-biased E-B junction injects minority carriers (electrons for NPN) into the base — a thin p-type region (W_B ≪ L_n). Most injected electrons diffuse across the base without recombining and are swept into the collector by the reverse-biased C-B junction field. The fraction that recombines (base current) is small — β = Ic/Ib is large. β depends on: base width (thinner = less recombination = higher β), base doping (lower = less recombination = higher β), emitter doping (higher = more injection = higher β). β varies strongly with temperature (+~0.5%/°C) and current (falls at very low and very high Ic — Kirk effect at high current, emitter crowding). Ic ∝ exp(Vbe/Vₜ) — exponential I-V is fundamental to BJT log amplifiers, multipliers, and V-to-I converters.

The hybrid-π model linearises the BJT around its DC operating point (Q-point) for small AC signals (v ≪ Vₜ). Key parameters: gₘ = Ic/Vₜ — the transconductance, proportional to collector current. At Ic = 1 mA: gₘ = 38.7 mA/V. This is one of the most important numbers in analog design — higher gₘ means more gain per transistor. rπ = β/gₘ — input resistance, lower at higher current. rₒ = Va/Ic — output resistance due to base-width modulation (Early effect): collector current increases slightly with Vce because higher reverse bias widens the depletion region into the base, reducing effective W_B. fT (unity-current-gain frequency): the frequency at which current gain drops to 1 — characterises the transistor's speed. Modern SiGe HBTs achieve fT > 400 GHz.

The DC operating point (Q-point) must be stable against variations in β (50–500 range between units), temperature (Vbe drops ~2 mV/°C, Icbo doubles every 10°C), and power supply. The four-resistor emitter-degenerated bias achieves β-independent biasing: R1, R2 form a stiff voltage divider (stiff means R1||R2 ≪ β·Re); emitter resistor Re provides negative feedback that stabilises Ic. With β·Re ≫ R_th: Ic ≈ (V_B − 0.7)/Re — independent of β. Trade-off: Re reduces AC gain (unless bypassed with a capacitor). A good rule of thumb: set V_E ≈ Vcc/10 for good stability while preserving output swing. The Q-point stability problem is why MOSFET biasing is simpler — threshold voltage doesn't vary with ID the way Vbe varies with Ic.

Common-Emitter (CE): Voltage gain = −gₘRc (inverting), moderate input impedance. The workhorse for voltage amplification. At Ic = 1 mA with Rc = 10 kΩ: |Av| = 38.7 × 10k = 387. The Miller effect (Cμ reflected to input multiplied by gain) limits bandwidth. Common-Collector (CC / Emitter Follower): Voltage gain ≈ 1, current gain = β+1, output impedance ≈ 1/gₘ (very low — ~26 Ω at 1 mA). Used as buffer stages, impedance transformers. Drives capacitive loads without degrading the preceding stage. Common-Base (CB): Low input impedance (≈ 1/gₘ), high output impedance, no Miller effect (Cμ between output and grounded base). Used in RF cascode stages and current-input amplifiers. Cascoding CE with CB (the cascode) combines CE's high transconductance with CB's high output impedance, extending bandwidth.

The MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled device: a gate voltage applied through a thin oxide controls a conducting channel between source and drain. Physical structure: p-type substrate, thin SiO₂ gate insulator (down to 1 nm in modern nodes), heavily doped n+ source and drain. As gate voltage increases above threshold Vth, electrons are attracted to the Si-SiO₂ interface, forming an inversion layer — a thin conducting channel of electrons in p-type silicon. Vth depends on: oxide thickness (thinner oxide → lower Vth for same charge); body doping (higher Na → larger depletion charge → higher Vth); trapped charges in oxide; and body bias (bulk-source voltage). In modern CMOS, Vth is set by ion implantation (threshold adjust implant) typically to 0.3–0.7 V.

In the linear (triode) region (Vds < Vgs−Vth): the MOSFET behaves as a voltage-controlled resistor — Ron = 1/[μCox(W/L)(Vgs−Vth)]. Used as a switch (minimal Ron) and as a resistor in analog designs. In saturation (Vds ≥ Vgs−Vth): current is controlled by Vgs and is nearly independent of Vds — the transistor acts as a voltage-controlled current source (with finite output impedance 1/λId from channel-length modulation). Key insight: transconductance gₘ = ∂Id/∂Vgs = √(2μCox(W/L)Id) — gₘ ∝ √Id unlike BJT where gₘ = Ic/Vₜ ∝ Ic. For the same bias current, BJTs have higher gₘ than long-channel MOSFETs. In short-channel devices (modern nodes), velocity saturation causes Id ∝ (Vgs−Vth) rather than square law, and gₘ becomes proportional to W/L × Vov rather than its square root.

The MOSFET small-signal model has the same topology as the BJT hybrid-π but with: gate instead of base (infinite DC input impedance, no rπ); gmVgs current source; rₒ for channel-length modulation. fT (transit frequency) is the frequency where current gain magnitude falls to 1: fT ∝ μVov/L² — proportional to carrier mobility and overdrive voltage, inversely proportional to L². This is why scaling (reducing L) dramatically improves MOSFET speed. At L = 28 nm with Vov = 0.3 V: fT = (3/4π) × 400 × 0.3 / (28e-9)² ≈ 350 GHz. The maximum oscillation frequency fmax > fT in optimised devices. Cgd (gate-drain overlap) causes Miller effect in common-source amplifiers, reducing effective bandwidth — the cascode configuration eliminates this.

Common-Source (CS): The voltage amplifier — high input impedance (gate is oxide-isolated), voltage gain −gₘRd. At gₘ = 5 mA/V and Rd = 10 kΩ: |Av| = 50. Inverting. Bandwidth limited by Miller-multiplied Cgd. Common-Drain (Source Follower / CD): Buffer with near-unity voltage gain, very high input impedance, low output impedance ≈ 1/gₘ. Used to drive capacitive loads (LCD panels, cables). Unlike BJT emitter follower, MOSFET source follower has Vgs offset: Vout = Vin − Vgs — and Vgs depends on current (and thus load), causing nonlinearity. Common-Gate (CG): Current in, current (or voltage) out. Low input impedance, high output impedance. Used in cascode (stacked with CS) for high gain and bandwidth — the CS sets gₘ, the CG shields the CS from output, eliminating Miller effect and boosting Rout.

CMOS (Complementary MOS) pairs an NMOS and PMOS transistor — activated by complementary logic levels. The key CMOS advantage: zero static power — in steady state, one transistor is always off, blocking DC path from Vdd to GND. Only the minority subthreshold leakage flows. Power is consumed only during switching (dynamic power). This enabled the miniaturisation and integration density of modern digital electronics. The CMOS inverter is the fundamental building block: when Vin = 0 (logic L), PMOS is on (Vsg = Vdd > |Vthp|) pulling output to Vdd; NMOS is off. When Vin = Vdd (logic H), NMOS is on pulling output to 0; PMOS is off. Noise margins are excellent — nearly rail-to-rail output swing with sharp transitions. CMOS also enables complementary analog circuit techniques: PMOS loads for CS amplifiers (high output impedance without resistors), complementary differential pairs.

As channel length L shrinks below ~100 nm, the drain electric field penetrates toward the source, reducing the energy barrier for carrier injection — DIBL (Drain-Induced Barrier Lowering) reduces threshold voltage at high Vds, increasing Ioff. Subthreshold slope S (60 mV/decade at 300 K — the Boltzmann limit) determines how quickly the transistor turns off below Vth. With S = 60 mV/dec, reducing Vgs by 300 mV reduces Ioff by 5 decades. Scaling forces lower Vth for speed (higher Ion), but lower Vth means exponentially higher Ioff. This is the fundamental tension in modern CMOS: speed vs. leakage. Solutions: FinFET (3D gate wraps around channel, better electrostatic control, lower DIBL), Gate-All-Around (GAA) nanowire FETs (even better control). The 60 mV/dec Boltzmann limit on S is why tunnelling FETs and negative-capacitance FETs (ferroelectric) are being researched.

For a single-pole amplifier, the Gain-Bandwidth Product (GBW) is constant — increasing gain reduces bandwidth proportionally. Physical origin: bandwidth is set by the RC time constant at the high-impedance output node; gain = gₘ·Rout; bandwidth = 1/(2πRoutC). GBW = gₘ/(2πC) — independent of Rout. Higher bias current increases gₘ, increasing GBW. This is why high-bandwidth amplifiers consume more power. In an op-amp with dominant-pole compensation: GBW = gₘ/(2πCc). Typical values: 741 op-amp: GBW = 1 MHz; LM318: 15 MHz; OPA847: 3.9 GHz; SiGe HBT LNAs: > 100 GHz. Design trade-off: adding gain stages increases DC gain without reducing GBW per stage, but adds poles that can cause instability — the fundamental tension in feedback amplifier design.

The frequency response of any linear circuit is completely described by its poles (frequencies where gain drops 20 dB/decade per pole) and zeros (frequencies where gain rises 20 dB/decade). Poles arise from RC time constants: ωp = 1/RC. Zeros arise from parallel paths (a zero at the frequency where two paths cancel) or from series elements. Right-half-plane (RHP) zero: occurs in feedback amplifiers and switching converters (boost, flyback) — it adds phase lag (like a pole) while adding gain (like a left-half-plane zero). Particularly dangerous in feedback stability because it reduces phase margin while increasing gain. A zero at frequency fz in a boost converter: f_RHPZ = (1−D)²RL/(2πL) — forces compensation to roll off gain before this frequency. Miller's Theorem relates Cgd (between input and output of an inverting amplifier) to two capacitors: one at input (multiplied by gain) and one at output.

The differential pair is the most important building block in analog IC design. It amplifies the difference between two inputs while rejecting signals common to both — critical for noise immunity. CMRR (Common-Mode Rejection Ratio) quantifies how well common-mode signals (e.g., power supply noise, ground bounce) are rejected: CMRR = 20·log₁₀(Ad/Acm). A CMRR of 80 dB means common-mode signals are attenuated by 10,000× relative to differential signals. Tail current source: the key to CMRR — a high-impedance tail source means Acm ≈ 0 (the tail must carry the total current, suppressing common-mode response). In practice, CMRR is limited by transistor mismatch, tail impedance, and parasitic capacitances. Active current mirrors as tail sources (instead of resistors) achieve very high Rtail and thus high CMRR.

The ideal op-amp's infinite gain enables the virtual short principle: with negative feedback, the output adjusts to force V⁺ = V⁻. This makes closed-loop gain depend only on external feedback resistors — independent of the op-amp's own (variable, temperature-dependent) gain. This is the central power of feedback: component-independent precision. Real op-amp limitations that matter in practice: Input offset voltage Vos (0.1 μV–10 mV) — a small DC error voltage between inputs; critical for precision DC circuits. Input bias current Ib (1 pA–1 μA) — gate or base current that creates voltage drops across input resistors; use matched source impedances to cancel. Slew rate SR — maximum dV/dt the output can follow (limited by available current to charge compensation capacitor). Noise — Johnson noise of input stage resistances plus flicker (1/f) noise of transistors.

The beauty of op-amp circuits is that all closed-loop behaviour is set by passive components, exploiting the virtual-short principle. Inverting amplifier: input current flows through R1, output sources same current through R2; gain = −R2/R1 independent of op-amp gain. Input impedance = R1. Non-inverting: gain = 1 + R2/R1; input impedance = Rin_opamp (very high). Difference amplifier: requires accurate resistor matching for good CMRR — better to use an instrumentation amplifier (INA) which provides high Zin and adjustable gain with a single resistor. Integrator: the fundamental building block of active filters (state-variable filters), sigma-delta modulators, and PID control loops. Transimpedance amplifier (TIA): converts photodiode or sensor current to voltage — bandwidth limited by Rf·Cf and op-amp GBW; stability requires careful compensation. Used in optical receivers, current-sensing.

Slew Rate (SR): When the input signal changes faster than SR/(2π), the op-amp can't keep up — the output slews at maximum rate regardless of input, causing distortion. A 10 V peak sine wave at 1 MHz requires SR ≥ 2π×1×10⁶×10 ≈ 63 V/μs. Many general-purpose op-amps have SR = 0.5–1 V/μs — unusable at audio frequencies above a few kHz with any significant amplitude. Input offset voltage Vos: modelled as a small DC voltage source at one input; amplified by closed-loop gain. An inverting amplifier with gain 100 and Vos = 1 mV has 100 mV output error — fills the output range of a ±5V supply quickly. Use auto-zero or chopper-stabilised op-amps (Vos < 1 μV) for precision DC applications. Input bias current: BJT op-amps: Ib = 10 nA–1 μA; FET-input op-amps: Ib = 1–100 pA. Crucial for high-source-impedance sensors and charge amplifiers.

Negative feedback is the most powerful concept in electronics — it trades open-loop gain for: gain accuracy (closed-loop gain → 1/β, set by passive elements); bandwidth extension (BW_CL = BW_OL × (1+T)); reduced distortion (nonlinearity reduced by 1+T); reduced output impedance (series feedback); and increased input impedance (shunt feedback at input). The four feedback topologies (series-shunt, shunt-series, series-series, shunt-shunt) each sample a different output variable (voltage or current) and feed back a different signal (voltage or current) — and each has different effects on input and output impedance. Identifying the correct topology for a given circuit is essential for correct gain and impedance calculations. The price of feedback: potential instability — the loop gain must be managed to ensure adequate phase margin.

A feedback system oscillates when the loop gain T = Aβ = 1∠−180° — the feedback becomes positive at unity gain. Phase margin (PM) is how far from −180° the phase is when gain crosses 0 dB — larger PM means more stable but slower transient response. PM = 45° gives a quality factor Q = 1 (slight ringing); PM = 60° gives nearly critically damped response (preferred for most analog and power supply designs); PM < 30° gives ringing and possible instability with component variations. Gain margin (GM) is how much extra gain (in dB) would cause oscillation — typically required > 10 dB. Bode's stability criterion using straight-line approximations works well for dominant-pole systems. Two-pole systems are conditionally stable — three or more poles require careful compensation. The relationship: PM ≈ 90° − arctan(f_unity/fp2) for a two-pole system with dominant pole fp1 and non-dominant pole fp2.

Dominant-pole (Miller) compensation: The standard two-stage op-amp technique. A capacitor Cc connected around the second gain stage (from its output back to its input) uses Miller multiplication to create a large effective capacitance at the first stage output — pushing the dominant pole to a very low frequency, ensuring |T(jω)| < 0 dB before the second pole is reached. This is pole-splitting: the dominant pole moves down, the non-dominant pole moves up. The RHP zero (at gₘ2/Cc) adds phase lag and must be controlled — either by ensuring f_unity ≪ fz_RHP, or by adding a series resistor Rz in series with Cc to place a LHP zero to cancel the RHP zero. Lead compensation: a zero added before the unity-gain frequency to add phase back. Used in power supply control loops. Cascode compensation: avoids the RHP zero entirely by using a different feedback path.

The Barkhausen criterion states that steady-state oscillation requires: loop gain magnitude = 1 AND total phase shift around the loop = 0° (or 360°). Startup requirement: the loop gain must initially exceed 1 (typically 2–3×) to allow oscillations to build from noise — as amplitude grows, nonlinearity (transistor saturation/cutoff) naturally reduces gain to exactly 1. This automatic gain control is inherent to all practical oscillators. Phase condition determines frequency: the oscillator oscillates at the frequency where the total phase shift is 0°. LC networks provide sharp phase transitions at resonance — allowing precise frequency selection. RC oscillators (Wien bridge, phase shift) achieve 0° phase with RC networks — less precise (Q ≈ 1) but simpler and work at audio frequencies. Q factor determines phase noise — higher Q means steeper phase slope near resonance, reducing sensitivity to noise-induced phase perturbations.

LC oscillators use a resonant tank circuit (inductor + capacitors) to set frequency. The tank's high Q provides both the phase shift needed for oscillation and the filtering that suppresses harmonics and noise. Colpitts oscillator: capacitive voltage divider (C1, C2 in series between drain and source with their junction connected to a common node) provides feedback; the ratio C1/C2 sets the feedback fraction. Widely used in RF oscillators from kHz to GHz. Hartley: uses inductive divider instead — tapped inductor. Clapp: Colpitts variant with an additional series capacitor Cs in series with the inductor — Cs dominates the tuning, making frequency less sensitive to transistor parasitic capacitances. Better frequency stability than Colpitts. Cross-coupled pair (LC VCO): the most common topology in CMOS RFICs — two inverters (or differential pairs) cross-coupled to provide −gₘ negative resistance to overcome tank losses. Varactors tune frequency in PLLs.

Crystal oscillators: A quartz crystal is a piezoelectric resonator with Q = 10,000–100,000 — orders of magnitude higher than any LC tank. The high Q means the phase slope at resonance is extremely steep, making the oscillation frequency extremely insensitive to circuit variations (temperature, supply, transistor changes). Frequency stability: ±20 ppm (standard); ±0.5 ppm (TCXO — temperature compensated); ±0.01 ppb (OCXO — oven-controlled). Crystal frequency is set by mechanical dimensions — essentially immune to circuit noise. Phase-Locked Loop (PLL): a feedback system that locks a VCO to a reference frequency through a phase detector and loop filter. Frequency synthesis: fout = (N/R)·fref — integer or fractional-N ratios allow almost any output frequency from one reference. PLLs multiply frequency while adding their own phase noise; reference noise is multiplied by N². Used in virtually every wireless device, processor clock generator, and frequency synthesiser.

Thermal noise (Johnson-Nyquist): random thermal motion of electrons in any resistor — unavoidable, present in all conductors. White spectrum up to THz. An RMS noise voltage Vn = √(4kTRB). At room temperature, a 1 kΩ resistor in 1 Hz bandwidth: Vn = √(4×1.38e-23×300×1000) ≈ 4 nV/√Hz. Shot noise: discrete nature of charge carriers crossing a junction — Poisson process. In a photodetector at 1 mA: In = √(2×1.6e-19×1e-3) ≈ 18 pA/√Hz. Flicker (1/f) noise: from trapping and release of carriers at semiconductor surface/oxide interface defects. Dominates at low frequencies — critical for audio circuits, precision DC, and oscillator phase noise close to carrier. MOSFETs have much worse 1/f noise than BJTs (polysilicon gate creates more interface states). BJTs preferred for low-frequency precision analog (op-amps, audio front-ends). Chopper techniques and auto-zeroing can effectively eliminate 1/f noise.

Noise Figure (NF) quantifies how much an active stage degrades the signal-to-noise ratio — 0 dB is ideal (no added noise). In a cascade (LNA → mixer → IF amplifier → ADC), the Friis formula shows that the first stage's noise figure and gain dominate the system NF: the first stage's noise is not amplified, but all subsequent stages' noise is divided by the accumulated gain before them. Design implication: the LNA (Low-Noise Amplifier) is the most critical block in a receiver — it must have low NF (typically 0.5–2 dB) and adequate gain (10–20 dB) to suppress the noise of later stages. A 15 dB gain LNA with NF = 1 dB followed by a mixer with NF = 10 dB: F_total ≈ F_LNA + (F_mixer−1)/G_LNA = 1.26 + (10−1)/31.6 ≈ 1.54 → NF_total = 1.9 dB. Without the LNA, NF = 10 dB — a 8 dB degradation in sensitivity.

Power amplifier classes describe the transistor conduction angle — how many degrees of the input cycle the transistor conducts. Class A: transistor always conducting — biased at mid-point, linear but maximum 50% efficiency (half the DC power is always dissipated even with no signal). Used where linearity is paramount: audio amplifiers, linear RF transmitters. Class B: two complementary transistors each conducting half-cycle — 78.5% efficiency but crossover distortion at zero crossing. Class AB: small quiescent current eliminates crossover distortion; the standard for audio power amplifiers. Class D: switch-mode — transistors switch between fully on and fully off (efficiency > 90%) — dominates modern audio (smartphone speakers, soundbars) and motor drives. PWM signal reconstructed by output LC filter. Class E/F: used in RF transmitters — circuit conditions designed so transistor switches with zero voltage or zero current (ZVS/ZCS), minimising switching losses; efficiencies > 95% at GHz frequencies possible.

Switching regulators achieve high efficiency by operating transistors as switches (not linear elements). The inductor stores and releases energy; the capacitor filters the output. Buck converter: steps voltage down (Vout = D·Vin). The MOSFET switch chops Vin at duty cycle D; the LC filter averages to D·Vin. Boost: steps voltage up — when switch is on, inductor stores energy from Vin; when off, inductor forces current through the diode to a higher output voltage. Key design choices: switching frequency f_sw sets inductor and capacitor size (higher f_sw → smaller L, C) but increases switching losses (proportional to f_sw). Modern silicon MOSFETs operate efficiently at 100 kHz–5 MHz; GaN devices enable 10–100 MHz switching. Feedback loop design (Type II or Type III compensator) must stabilise the converter with adequate phase margin over load and line variations — including managing the RHP zero of boost and buck-boost converters.

Linear regulators dissipate excess power as heat: P_dissipated = (Vin − Vout)×Iout. Efficiency η = Vout/Vin — low when Vin ≫ Vout. Used where: noise-sensitive circuits need clean supply (PSRR > 60 dB up to MHz); output ripple must be extremely low (ADC reference, PLL supply); simplicity and small size outweigh efficiency concerns. LDO (Low Drop-Out): uses a p-channel MOSFET (or PNP BJT) as the pass element — gate at lower potential than source, allowing dropout as low as 50–200 mV. NMOS-based LDOs can achieve <50 mV dropout but require a charge pump for gate drive. Stability: LDOs with a large output capacitor (typically 10 μF ceramic) form a feedback loop with the pass element and error amplifier — the output capacitor's ESR creates a zero; careful placement of this zero relative to the unity-gain frequency ensures stability. MLCC capacitors have very low ESR — may require an ESR range specification or internal compensation.

MOSFET gate drive is critical for efficient switching. The gate is a capacitor — charging it to Vgs_on requires current; discharge to turn off. Gate charge Qg (from datasheet) characterises total drive energy per cycle. The Miller plateau in the gate waveform — a flat region during switch-on where Vgs stays constant while Qgd is supplied — is the critical switching transition: the MOSFET is in saturation, carrying full drain current with significant Vds, causing large instantaneous power dissipation. Fast gate drive (low Rg) speeds through this interval, reducing P_sw. But too-fast gate drive causes high dI/dt, leading to EMI, voltage spikes from parasitic inductance (L·dI/dt), and ringing. Dead-time in half-bridge circuits (brief period where both MOSFETs are off) prevents shoot-through (both transistors simultaneously conducting, short-circuiting the supply). Too-long dead-time forces body diode conduction (lossy, slow recovery in Si MOSFETs; much better in GaN GIT devices).

CMOS dominates digital logic because: near-zero static power (only subthreshold leakage); rail-to-rail output swing (full noise margins); scalable (smaller transistors → lower CL → faster, lower power). Dynamic power P = α·CL·Vdd²·f dominates at speed — reducing Vdd by 2× reduces power by 4×, the driving force behind voltage scaling (from 5V TTL to 0.6V advanced CMOS). Historical logic families for context: TTL (transistor-transistor logic) — bipolar, 10 mW/gate static power, fast but current-hungry; ECL (emitter-coupled logic) — fastest bipolar (~100 ps), but enormous static power (100 mW/gate), used only where speed is paramount (old mainframes, some RF). LVDS (Low Voltage Differential Signalling) — CMOS-friendly differential standard for high-speed data links (up to multi-Gbps). Modern standards (PCIe, DDR5, LPDDR5) are all CMOS-based differential schemes for energy efficiency at >10 Gbps.

Modern processors are essentially leakage-and-capacitance power problems at scale. With 100 billion transistors switching at GHz rates: Dynamic power (α·C·Vdd²·f) dominates at high frequency and high voltage — why CPU cores use dynamic voltage and frequency scaling (DVFS), reducing both Vdd and f during low-load periods. Short-circuit power (Isc during input transitions when both NMOS and PMOS briefly conduct simultaneously): minimised by fast input transitions and proper sizing. Leakage power: exponentially sensitive to Vth and temperature — in advanced nodes at high temperature, leakage can exceed dynamic power in idle circuits. Multi-Vth design: uses a mix of high-Vth cells (low leakage, slow) on non-critical paths and low-Vth cells (fast, higher leakage) on critical paths — optimising the speed-leakage trade-off. Power gating (cutting off supply to idle blocks) reduces leakage by orders of magnitude.

SRAM (6-transistor): Two cross-coupled CMOS inverters (4T) latch to stable '0' or '1'; two access transistors connect to bit lines for read/write. No refresh needed. Extremely fast (sub-ns access). Area-intensive (6 transistors). Used for: processor caches (L1, L2, L3), register files, fast buffers. DRAM (1T1C): One transistor selects the storage capacitor; charge on the capacitor represents '1'. Smallest bit cell — enables gigabyte densities. Requires periodic refresh (charge leaks in ~64 ms). Slower than SRAM. Sensitive to alpha-particle soft errors (cosmic radiation ionises Si, depositing charge on storage capacitor — error correction needed in DDR). NAND Flash: floating gate (or charge-trap layer) between control gate and channel traps charge; Vth shift encodes data. MLC (2 bits/cell), TLC (3 bits/cell), QLC (4 bits/cell) trade endurance (P/E cycles) for density. NVM endurance: SLC: 100,000 cycles; QLC: ~100 cycles. Used for SSDs, smartphones, IoT firmware.

The Nyquist theorem states that a signal sampled at f_s can be perfectly reconstructed if it contains no frequency components above f_s/2 (the Nyquist frequency). Signals above f_s/2 are aliased — they fold back into the baseband, corrupting the spectrum irreversibly. Anti-aliasing filter (AAF): a low-pass filter placed before the ADC input that attenuates signals above f_s/2. The filter's rolloff must ensure that aliased components fall below the ADC's noise floor. For a 16-bit ADC, the alias must be < −96 dB — a very steep filter requirement. Oversampling: sampling at k×f_s (k ≫ 1) relaxes the AAF requirement dramatically — a gentle filter suffices since the first alias is at k·f_s − f_signal, far from the signal band. Sigma-delta ADCs oversample by 64–512× and use digital decimation filters — allowing extremely linear, high-resolution conversion with very simple analog anti-aliasing. Used in audio, precision instrumentation, 24-bit measurement.

Flash ADC: 2^N − 1 comparators compare Vin simultaneously against every reference voltage — fastest possible (single clock cycle), used at > 1 GSPS for oscilloscopes and radar. Power and area scale as 2^N — only practical to 8–10 bits. SAR ADC: successive approximation — binary search with a DAC and one comparator. Moderate speed (1–100 MSPS), excellent power efficiency (1–10 mW), 12–18 bits. Dominates IoT, microcontroller ADCs. Pipeline ADC: flash sub-ADC stages in sequence, each resolving 1–4 bits and passing the residue amplified to the next stage — high speed (100 MSPS–1 GSPS), 10–16 bits. Used in wireless infrastructure, medical imaging. Sigma-Delta (ΣΔ): oversampled, uses noise shaping to push quantisation noise to high frequencies, then decimation filters remove it — 16–24 bit resolution at audio/measurement speeds. An ideal N-bit ADC has SNR = 6.02N + 1.76 dB; real converters fall short (ENOB < N) due to comparator noise, timing jitter, nonlinearity.

R-2R Ladder DAC: Simple resistor network with only two resistor values — binary-weighted current divider. Easy to implement; accuracy limited by resistor matching. Used in low-to-moderate resolution applications. Current-steering DAC: binary-weighted or thermometer-coded current sources switched to output — fastest DAC architecture (multi-GSPS). Used in RF DACs for direct digital synthesis (DDS). Key challenge: unit current source matching (σ_I/I) limits ENOB. For 12 bits: need matching to 1/(4096) = 0.024%. Achievable with careful layout (common-centroid) and current calibration. Glitch energy: during major code transitions (e.g., 0111…1 → 1000…0), multiple bits switch simultaneously — momentary current imbalance creates a glitch spike. Deglitch circuit (sample-and-hold) or thermometer coding (equal-sized unit cells, monotonic) reduces glitch. ΣΔ DAC: 1-bit DAC oversampled at high rate, noise-shaped — 24-bit audio quality from extremely simple analog hardware.

An OTA (Operational Transconductance Amplifier) converts an input voltage difference to an output current — Iout = Gm·ΔVin — with a high-impedance output (unlike a conventional op-amp which has low output impedance). The OTA's transconductance Gm is proportional to its bias current: Gm = gₘ = 2Id/Vov for MOSFET, or Ic/Vₜ for BJT. Tunability: by varying the bias current, Gm can be adjusted electrically — enabling electronically tunable filters and variable-gain amplifiers. Gm-C filters: replace capacitor-resistor integrators (op-amp + resistor + capacitor) with OTA + capacitor — the OTA provides the transconductance, C integrates. The time constant τ = C/Gm can be tuned by adjusting bias current, enabling programmable filters for software-defined radio and adaptive equalisation. Used extensively in continuous-time sigma-delta ADCs and baseband analog signal chains.

Current mirrors copy a reference current to one or more outputs — fundamental to biasing every transistor in an analog IC. Basic mirror: Iout/Iref = (W/L)2/(W/L)1 for MOSFET, or (Is2/Is1) for BJT. Error sources: Vds mismatch (from different output nodes) causes ΔI via channel-length modulation; threshold voltage mismatch (random, from process); temperature differences. Cascode mirror: adds cascode transistors to present equal Vds to both reference and output devices — dramatically improves accuracy and output impedance (Rout ≈ gₘ·rₒ²). Active loads: replacing drain resistors with current mirrors creates differential-pair amplifiers with very high voltage gain — the cascode mirror active load is the standard topology in op-amp first stages, achieving Av = gₘ·(rₒN||rₒP) ≈ 50–200 V/V per stage with open-loop gain of 10,000+ V/V overall.

A bandgap voltage reference exploits the cancellation of two opposing temperature dependencies in silicon: CTAT (Complementary To Absolute Temperature): Vbe decreases at ~−2 mV/°C (CTAT). PTAT (Proportional To Absolute Temperature): the difference ΔVbe between two BJTs at different current densities is PTAT: ΔVbe = (kT/q)·ln(n) ∝ T. Adding a scaled PTAT voltage to Vbe, with the right scaling factor, cancels the temperature dependence at their sum ≈ Eg/q ≈ 1.205 V. Result: a reference that is stable to ±1–10 ppm/°C over −40°C to +125°C — without any external calibration. The bandgap reference is in every precision ADC, DAC, LDO regulator, temperature sensor, and analog IC. In CMOS processes, substrate BJTs (parasitic PNP transistors) are used — their parameters are less ideal but sufficient.

Charge pumps: generate voltages above (or below) the supply using capacitors and switches — no inductors. The Dickson pump adds Vclk to each stage: Vout ≈ Vin + N·Vclk (minus threshold drops). Used for: Flash EEPROM programming (need 15–20 V from 3.3 V supply), MOSFET gate bias in LDOs, LCD bias voltages, SRAM cell boost. Efficiency limited by capacitor charging losses and threshold drops. Switched-capacitor (SC) circuits: a capacitor switched between two voltages at frequency f_clk emulates a resistor of value 1/(f_clk·C) — enabling resistors to be replaced by capacitors and switches in CMOS (which has excellent capacitor accuracy but poor resistor accuracy). SC filters, integrators, and amplifiers achieve very precise time constants set by capacitor ratios (accurate to 0.1%) and clock frequency. Foundation of most precision CMOS ADCs (including SAR and ΣΔ) and programmable filters.

The PLL is a phase-tracking feedback system: phase detector compares output (divided by N) to reference, producing an error signal filtered by F(s) and applied to the VCO. In lock, the phase error is zero and fout = N·fref. Noise analysis: reference phase noise and phase detector noise are multiplied by N² (high-pass filtered, so at frequencies below loop bandwidth these dominate). VCO phase noise (which degrades 20 dB/decade below the carrier) is suppressed by the loop at frequencies below ωn — but passes through at high offset frequencies. The PLL bandwidth must be chosen to minimise total integrated phase noise. Fractional-N PLL: by alternating division between N and N+1 (using a delta-sigma modulator), fractional frequency multiplication achieves very fine frequency resolution. Modern RFICs use fractional-N PLLs for sub-Hz frequency resolution from multi-GHz oscillators.

RF CMOS LNA design is the art of achieving simultaneously: low noise figure, 50 Ω input matching, adequate gain, and reasonable power consumption. Inductively degenerated LNA: adding Ls at the source creates a real input impedance Rin = ωT·Ls — set to 50 Ω — without using a resistor (which would add noise). Lg resonates with Cgs and Ls to set the operating frequency: ω₀² = 1/((Lg+Ls)·Cgs). The minimum achievable noise figure (NFmin) improves with higher fT — motivation for using advanced CMOS nodes (fT > 300 GHz at 16 nm) or SiGe BiCMOS for RF. Matching for minimum NF (noise matching, at Γopt) differs from power matching (at Γin* = conjugate of 50 Ω) — LNA designers must choose between best NF or best power transfer; often a compromise near Γopt is chosen. Noise-cancelling LNAs use a second amplifier path to cancel amplifier noise while adding signal.

III-V compound semiconductors outperform silicon in key parameters — high electron mobility, direct bandgaps (enabling light emission), and high breakdown voltages. GaAs: 6× higher electron mobility than Si — enables lower-noise and higher-frequency transistors. Used in cell phone power amplifiers (PA), satellite receivers, millimetre-wave radar. InP HBT: Heterojunction Bipolar Transistor — graded bandgap improves minority carrier injection efficiency; fT > 500 GHz, fmax > 1 THz achieved. Used in optical fibre ICs (100–400 Gb/s) and sub-THz imaging. HEMT (High Electron Mobility Transistor): a 2D electron gas (2DEG) forms at the AlGaAs/GaAs (or AlGaN/GaN) interface — electrons confined to a narrow channel away from doping atoms, experiencing much less scattering. Extremely high mobility (μ > 8000 cm²/Vs at 300 K for AlGaAs/GaAs). SiGe HBT BiCMOS integrates high-performance SiGe HBTs with standard CMOS on the same die — the dominant technology for RF ICs at 1–100 GHz.

Wide-bandgap (WBG) semiconductors offer critical electric field strengths 5–10× higher than silicon, enabling the same breakdown voltage at much thinner (and more lightly doped) drift regions — dramatically reducing on-resistance (Baliga FOM: σ ∝ μ·ε·E_crit³). SiC MOSFETs: 10× lower specific on-resistance vs Si for the same breakdown voltage; high thermal conductivity (3× Si) allowing compact high-power designs. 650–3300 V switches for EV drivetrains, solar inverters, industrial motor drives. SiC SBDs (Schottky Barrier Diodes): no minority carrier storage → zero reverse recovery → enables high-frequency, high-efficiency rectification. GaN HEMTs: on Si substrates (lower cost), 650 V capable, extremely fast switching (10× faster than Si MOSFETs at same rating), very low gate charge. Dominates AC-DC adapters (GaN enables 200 W chargers the size of a phone charger), 5G base station PAs, LIDAR drivers. Diamond (Eg = 5.5 eV) and Ga₂O₃ (Eg = 4.9 eV) are next-generation WBG materials in research.

Power MOSFET (VDMOS, superjunction): vertical structure — current flows vertically through a lightly doped drift region whose width determines breakdown voltage. The drift region dominates Rdson at > 100 V: Rdson_drift ∝ V_break^2.5 for Si — rapidly increasing with voltage, eventually making Si MOSFETs uncompetitive vs IGBTs above ~900 V. Superjunction (coolMOS): alternating n and p columns in the drift region allow high doping without sacrificing breakdown — Rdson ∝ V_break^1.3, dramatically improving high-voltage Si MOSFETs. IGBT (Insulated Gate Bipolar Transistor): MOSFET + BJT in series — the MOSFET gate controls a PNP bipolar transistor. Minority carrier (bipolar) conductivity modulation reduces on-state voltage drop from Rdson·Id to ~2 V regardless of current — much better than a MOSFET at > 600 V. Trade-off: bipolar minority charge must be swept out during turn-off — slow switching (1–20 μs), lossy for high-frequency operation. IGBTs dominate: 1200–6500 V industrial drives, EV traction inverters, UPS, grid converters.

Thermal design follows the exact analogy of an electrical circuit: power dissipation (W) ↔ current (A); temperature (K) ↔ voltage (V); thermal resistance (K/W) ↔ resistance (Ω); heat capacity (J/K) ↔ capacitance (F). Rθ_jc (junction-to-case): determined by die size and package — from 0.1 K/W (large power module) to 50 K/W (SOT-23). Rθ_cs: thermal interface material between package and heatsink — 0.01–0.1 K/W with good TIM. Rθ_sa: heatsink to ambient — 0.5–10 K/W depending on size and airflow. Maximum junction temperature: 150°C (Si MOSFET), 175°C (SiC MOSFET), 200°C (SiC JFET/diode). Every 10°C rise in Tj halves the electromigration failure rate — thermal design is reliability design. Transient thermal impedance (Zth_jc vs. pulse width) allows calculation of peak junction temperature for short current pulses — enabling safe operation well above DC ratings for pulsed loads.

Modern CMOS fabrication (e.g., TSMC N3, Intel 18A) involves ~1000 process steps over 2–3 months. Key steps: STI (Shallow Trench Isolation): oxide-filled trenches electrically isolate transistors. Gate stack formation: thermal SiO₂ replaced by high-k (HfO₂, εr≈25) + metal gate at 45 nm node — eliminates gate leakage and poly depletion. Ion implantation: dopants implanted at controlled energy (depth) and dose; activated by rapid thermal anneal (RTA, 1000°C, 1 sec). EUV lithography (extreme ultraviolet, λ=13.5 nm) defines features < 10 nm. Cu damascene interconnect: trench etched in dielectric, filled with Cu, planarised by CMP — lower resistance than Al. Up to 15+ metal layers in advanced nodes. FinFET (Intel's Tri-gate, TSMC 16nm–7nm): 3D fin structure instead of planar channel — better gate control, lower leakage. Replaced by GAA (Gate-All-Around) nanosheets at 3 nm and below.

As feature sizes shrink, wire RC delay (not gate delay) has become the dominant performance limiter in large ICs. RC delay scales as: t ∝ ρ·ε·l²/(area ratio) — quadratically with length, a severe problem for global wires spanning the chip. Solutions: copper (ρ_Cu = 1.7 μΩ·cm vs. Al at 2.8 μΩ·cm, 40% lower) replaced aluminium at 130 nm. Low-k dielectrics (ε_r < 3, vs SiO₂ at 3.9) reduce capacitance — but mechanically fragile and thermally poor. Repeater insertion: breaking a long wire into segments with buffer inverters at optimal intervals reduces t from O(l²) to O(l) — at the cost of area and power. Resistivity crisis: as Cu wire dimensions approach electron mean free path (~40 nm), grain boundary and surface scattering increase ρ dramatically — ρ at W=10 nm is 3–5× bulk ρ_Cu. Alternative metals (Ru, Mo, Co) being explored for ultra-fine wires at <5 nm pitch.

IC reliability is fundamentally about managing physical failure mechanisms that are accelerated by temperature, current density, and electric field. Electromigration (EM): metal ion migration driven by electron momentum transfer — copper atoms accumulate at flux divergence points, forming voids (opens) or hillocks (shorts). MTF ∝ 1/J² × exp(Ea/kT). Limit: J_max ≈ 10 MA/cm² for Cu interconnects at 105°C. TDDB (gate oxide breakdown): traps accumulate in gate oxide under field stress; after time T_BD, a percolation path forms — instantaneous gate shorting. Limits Vdd and minimum oxide thickness. NBTI (Negative Bias Temperature Instability): PMOS Vth shifts positive under negative gate bias at elevated temperature — reduces Ion over time, causing timing failures in digital circuits. Recovered partially when bias removed (AC stress). HCI (Hot Carrier Injection): hot carriers from high-field channel inject into gate oxide, shifting Vth and degrading gₘ. Most severe at moderate Vds/Vgs during switching.

CMOS scaling faces multiple fundamental limits. Boltzmann subthreshold slope limit (60 mV/dec): cannot be beaten in a classical transistor at any finite temperature — even with perfect electrostatics, reducing Vgs by 60 mV reduces Ioff by 10×. Lower Vth (for speed) inevitably raises Ioff. Solutions being pursued: Tunnel FETs (TFETs) exploit quantum tunnelling — can achieve S < 60 mV/dec, but limited Ion; Negative Capacitance FETs (NCFETs) using ferroelectric gate materials; 2D materials (graphene, MoS₂) for ultra-thin channels. 3D integration: stacking chiplets (HBM memory, DRAM, logic) with through-silicon vias (TSVs) and hybrid bonding (Cu-Cu direct bonding at 1–10 μm pitch) — already in production (AMD 3D V-Cache, HBM3). Neuromorphic and in-memory computing: moving computation to where data is stored, using analog charge states — circumventing the von Neumann memory bottleneck. Quantum computing: superconducting qubits at millikelvin temperatures — not replacing CMOS but solving classically intractable problems (optimisation, quantum chemistry).